////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 10.1
//  \   \         Application : sch2verilog
//  /   /         Filename : FinalResult.vf
// /___/   /\     Timestamp : 12/13/2008 17:32:00
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: C:\Xilinx\10.1\ISE\bin\nt\unwrapped\sch2verilog.exe -intstyle ise -family spartan3e -w "C:/Documents and Settings/William Lee/My Documents/cs3710/CR16/FinalResult.sch" FinalResult.vf
//Design Name: FinalResult
//Device: spartan3e
//Purpose:
//    This verilog netlist is translated from an ECS schematic.It can be 
//    synthesized and simulated, but it should not be modified. 
//
`timescale 1ns / 1ps

module FinalResult(clock, 
                   controller1, 
                   controller2, 
                   reset, 
                   controllerPower, 
                   controllerSelect, 
                   hSyncOut, 
                   LED, 
                   VGAout, 
                   vSyncOut);

    input clock;
    input [5:0] controller1;
    input [5:0] controller2;
    input reset;
   output controllerPower;
   output controllerSelect;
   output hSyncOut;
   output [15:0] LED;
   output [5:0] VGAout;
   output vSyncOut;
   
   wire [15:0] memAddress;
   wire XLXN_2;
   wire [15:0] XLXN_9;
   wire [15:0] XLXN_13;
   wire XLXN_14;
   wire XLXN_15;
   wire XLXN_16;
   wire XLXN_17;
   wire [15:0] XLXN_19;
   wire XLXN_20;
   wire XLXN_21;
   wire [15:0] XLXN_25;
   wire [15:0] XLXN_26;
   wire [15:0] XLXN_28;
   wire [15:0] LED_DUMMY;
   
   assign LED[15:0] = LED_DUMMY[15:0];
   Top XLXI_1 (.clock(clock), 
               .memData(XLXN_28[15:0]), 
               .reset(reset), 
               .memAddress(memAddress[15:0]), 
               .memEnable(XLXN_15), 
               .writeData(XLXN_19[15:0]), 
               .writeMemEnable(XLXN_17));
   controller2 XLXI_2 (.clock(XLXN_2), 
                       .controllerIn(controller2[5:0]), 
                       .reset(reset), 
                       .controllerOut(XLXN_25[15:0]), 
                       .controller2Enable(XLXN_21));
   ControllerReg XLXI_3 (.clock(XLXN_2), 
                         .controller(controller1[5:0]), 
                         .reset(reset), 
                         .controllerOut(LED_DUMMY[15:0]), 
                         .controllerSelect(controllerSelect), 
                         .controller1Enable(XLXN_20), 
                         .power(controllerPower));
   memoryMapped XLXI_4 (.address(memAddress[14:12]), 
                        .controller1(XLXN_20), 
                        .controller1Data(LED_DUMMY[15:0]), 
                        .controller2(XLXN_21), 
                        .controller2Data(XLXN_25[15:0]), 
                        .en(XLXN_15), 
                        .memData(XLXN_26[15:0]), 
                        .memDataOut(XLXN_28[15:0]), 
                        .memEnable(XLXN_16));
   TestRAM XLXI_5 (.clock(XLXN_2), 
                   .Enable(XLXN_16), 
                   .Enable2(XLXN_14), 
                   .memAddress(memAddress[15:0]), 
                   .vgaAddress(XLXN_9[15:0]), 
                   .writeData(XLXN_19[15:0]), 
                   .writeEnable(XLXN_17), 
                   .memData(XLXN_26[15:0]), 
                   .vgaData(XLXN_13[15:0]));
   VGA_sch XLXI_6 (.clock(XLXN_2), 
                   .memoryData(XLXN_13[15:0]), 
                   .reset(reset), 
                   .hSyncOut(hSyncOut), 
                   .memEnable(XLXN_14), 
                   .VGAaddress(XLXN_9[15:0]), 
                   .VGAout(VGAout[5:0]), 
                   .vSyncOut(vSyncOut));
   INV XLXI_7 (.I(clock), 
               .O(XLXN_2));
endmodule
